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DISCRETE SEMICONDUCTORS
DATA SHEET
PHP225 Dual P-channel enhancement mode MOS transistor
Product specification Supersedes data of November 1994 File under Discrete Semiconductors, SC13b 1997 Jun 20
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
FEATURES * High-speed switching * No secondary breakdown * Very low on-resistance. APPLICATIONS * Motor and actuator driver * Power management * Synchronized rectification. DESCRIPTION Two P-channel enhancement mode MOS transistors in an 8-pin plastic SOT96-1 (SO8) package. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling.
1 4 s1 g 1 d1 d1 5
PHP225
PINNING - SOT96-1 (SO8) PIN 1 2 3 4 5 6 7 8 SYMBOL s1 g1 s2 g2 d2 d2 d1 d1 DESCRIPTION source 1 gate 1 source 2 gate 2 drain 2 drain 2 drain 1 drain 1
handbook, halfpage
d2 d2
8
MAM119
s2
g
2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA SYMBOL Per P-channel VDS VSD VGSO VGSth ID RDSon Ptot drain-source voltage (DC) source-drain diode forward voltage gate-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance total power dissipation ID = -1 A; VGS = -10 V Ts = 80 C IS = -1.25 A open drain ID = -1 mA; VDS = VGS - - - -1 - - - -30 -1.6 20 -2.8 -2.3 0.25 2 V V V V A W PARAMETER CONDITIONS MIN. MAX. UNIT
1997 Jun 20
2
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Per P-channel VDS VGSO ID IDM Ptot drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation open drain Ts 80 C note 1 Ts = 80 C; note 2 Tamb = 25 C; note 3 Tamb = 25 C; note 4 Tamb = 25 C; note 5 Tstg Tj IS ISM Notes 1. Pulse width and duty cycle limited by maximum junction temperature. storage temperature operating junction temperature Ts 80 C note 1 - - - - - - - - -65 - - - -30 20 PARAMETER CONDITIONS MIN.
PHP225
MAX.
UNIT
V V A A W W W W C C
-2.3 -10 2 2 1 1.3 +150 150 -1.25 -5
Source-drain diode source current (DC) peak pulsed source current A A
2. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 2 W at the same time. 3. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 5. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W.
1997 Jun 20
3
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
PHP225
handbook, halfpage
2.5
MLB836
2 10 handbook, halfpage
MBE155
P tot (W)
ID (A) 10 (1) tp = 10 s
2.0
1.5 1 1.0 10 0.5 tp T 0 0 50 100 150 T s ( oC) 200 10
2 1 1
1 ms P
= T
tp DC 0.1 s
t
10
1
10
V
DS
(V)
10 2
= 0.01. Ts = 80 C. (1) RDSon limitation.
Fig.2 Power derating curve.
Fig.3 SOAR.
1997 Jun 20
4
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER thermal resistance from junction to soldering point VALUE 35
PHP225
UNIT K/W
CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL Per P-channel V(BR)DSS VGSth IDSS IGSS IDon RDSon yfs Ciss Coss Crss QG QGS QGD drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current on-state drain current drain-source on-state resistance forward transfer admittance input capacitance output capacitance reverse transfer capacitance total gate charge gate-source charge gate-drain charge VGS = 0; ID = -10 A VGS = VDS ; ID = -1 mA VGS = 0; VDS = -24 V VGS = 20 V; VDS = 0 VGS = -10 V; VDS = -1 V VGS = -4.5 V; VDS = -5 V VGS = -4.5 V; ID = -0.5 A VGS = -10 V; ID = -1 A VDS = -20 V; ID = -1 A VGS = 0; VDS = -20 V; f = 1 MHz VGS = 0; VDS = -20 V; f = 1 MHz VGS = 0; VDS = -20 V; f = 1 MHz VGS = -10 V; VDS = -15 V; ID = -2.3 A VGS = -10 V; VDS = -15 V; ID = -2.3 A VGS = -10 V; VDS = -15 V; ID = -2.3 A VGD = 0 to -10 V; VDD = -20 V; ID = -1 A; RL = 20 VGS = -10 to 0 V; VDD = -20 V; ID = -1 A; RL = 20 VGD = 0; IS = -1.25 A IS = -1.25 A; di/dt = 100 A/s -30 -1 - - -2.3 -1 - - 1 - - - - - - - - - - - - 0.33 0.22 2 250 140 50 10 1 3 - -2.8 -100 100 - - 0.4 0.25 - - - - 25 - - V V nA nA A A S pF pF pF nC nC nC PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Switching times ton toff turn-on time turn-off time - - 20 50 80 140 ns ns
Source-drain diode VDS trr source drain diode forward voltage reverse recovery time - - - 150 -1.6 200 V ns
1997 Jun 20
5
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
, g
PHP225
MBE144
handbook, halfpage
600
10 ID (A) 8
MBE154
VGS = 10 V
7.5 V
6V
C (pF) 400
6
C iss
5V 4.5 V
4
200 Coss
4V 2
C rss
3.5 V 3V 2.5 V 0 2 4 6 8 10 V DS (V) 12
0 0 10 20 V DS (V) 30
0
VGS = 0. Tj = 25 C. Tj = 25 C.
Fig.4
Capacitance as a function of drain-source voltage; typical values.
Fig.5 Output characteristics; typical values.
MBE157
handbook, halfpage
10
handbook, halfpage
10
MBE145
ID (A) 8
VGS (V)
8
6
6
4
4
2
2
0 0 2 4 6 V GS (V) 8
0 0 2 4 6 8 10 Q g (nC)
VDS = -10 V. Tj = 25 C.
VDD = -15 V. ID = -2.3 A.
Fig.7 Fig.6 Transfer characteristic; typical values.
Gate-source voltage as a function of total gate charge.
1997 Jun 20
6
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
PHP225
handbook, halfpage
6
MBE156
104 handbook, halfpage
MDA165
IS (A) 4
RDSon (m)
(1) (2)(3) (4) (5)
103
(1) (2) (3)
2
0 0 0.5 1 1.5 V SD (V) VGD = 0. (1) Tj = 150 C. (2) Tj = 25 C. (3) Tj = -55 C. 2
102
0
-2
-4
-6
-8 -10 VGS (V)
-VDS -ID x RDSon; Tj = 25 C. (1) ID = -0.1 A. (2) ID = -0.5 A. (3) ID = -1 A. (4) ID = -2.3 A. (5) ID = -4.5 A.
Fig.9 Fig.8 Source current as a function of source-drain diode forward voltage.
Drain-source on-state resistance as a function of gate-source voltage; typical values.
handbook, halfpage
1.2
MBE138
handbook, halfpage
1.8
MBE146
k 1.1
k 1.6
(1) (2)
1.0
1.4
0.9
1.2
0.8
1.0
0.7
0.8
0.6 50 0 50 100 T j ( C) V GSth at T j k = ------------------------------------V GSth at 25C Typical VGSth at ID = 1 mA; VDS =VGS = VGSth.
o
150
0.6 50 0 50 100 R DSon at T j k = ---------------------------------------R DSon at 25 C Typical RDSon at: (1) ID = -1 A; VGS = -10 V. (2) ID = -0.5 A; VGS = -4.5 V. T j ( C)
o
150
Fig.10 Temperature coefficient of gate-source threshold voltage.
Fig.11 Temperature coefficient of drain-source on-resistance.
1997 Jun 20
7
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
PHP225
10 2
MBE153
R th j-s (K/W)
= 0.75 0.5
10
0.33 0.2 0.1 0.05
1
0.02 0.01 0
P
= T
tp
tp T
t
10
1
10
6
10
5
10
4
10
3
10
2
10
1
t p (s)
1
Fig.12 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1997 Jun 20
8
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm
PHP225
SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 0.069 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024
0.028 0.004 0.012
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
1997 Jun 20
9
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
PHP225
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Jun 20
10
Philips Semiconductors
Product specification
Dual P-channel enhancement mode MOS transistor
NOTES
PHP225
1997 Jun 20
11
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
137107/00/02/pp12
Date of release: 1997 Jun 20
Document order number:
9397 750 02523

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